Complexity-effective Enhancements to a RISC CPU Architecture
نویسندگان
چکیده
The M•CORETM RISC architecture has been developed to address the growing need for long battery life among today’s embedded applications [4]. In this paper, we present several architectural enhancements to the M•CORE M3 processor. Specifically, we discuss the burst mode memory enhancements, the instruction fetch enhancements, the selectable branch prediction implementation, and the improvements for software patching. These additions to the M•CORE processor were carefully selected in order to increase performance at minimal cost and complexity, in order to meet the requirements of the portable, embedded marketplace.
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